rill analog w devices features ultra-high speed: 20mhz word rate 8- and 10-bit versions available ttl compatible smallest size available: 3" x 4" x 0.5" completely self.contained with input register, d/a, deglitcher, timing, internal references, and output buffering applications color-television video reconstruction, time-base cor- rection and frame synchronization . graphic displays deflection systems character generators high speed d/a systems general description the mdd series is a subsystem module which contains an input digital register, ultra-high speed current output d/a converter, deglitcher, output buffer amplifier~ precision refer- ences, and timing circuitry within a 3"x4"xo.s" case, the out- put of the device is an ultra-linear analog representation of the digital input. requiring only external gain and offset potentiometers for final calibration, the mdd d/a solves the . glitch problem associated with high-speed di a converters. the incorporation of an internal register virtually eliminates the need for input bit time deskewing. while not totally eliminat- ing the glitch per se, the remnant glitch is very smail, and more importantly, constant (and therefore filterable) over the out- put range, the mdd series is available with 8- or lo-bit resolution and in two versions. the basic versions contain a unity gain output buffer and can deliver zv pop open circuit (or 1 v pop into a load) when the mdd output is both source and load termin- ated. the "a" versions contain a very high speed output gain amplifier to allow the mdd to deliver 4v pop open circuit (or zv pop into a load) when the device is source and load termin- ated. higher output voltages may be obtained-up to :tlov by external feedback resistor selection. however, settling time degradation must be expected. tv application the "a" version of the mdd series deglitched di a is ideally suited for color television video reconstruction. its output can directly drive the low impedances normaily associated with video baseband transmission. since the output impedance of ultra high speed deglitched 0 / a converter mod series i the internal operational amplifier is less than h2, the transmis- sion-line match obtained with the internal source terminating resistor is almost perfect. other applications include waveform generation, automatic test equipment, and fast process con- trol systems. designed primarily for pc board mounting, these d/a's may also be plugged into pin sockets. the pins are 0,04" diameter, gold plated, and are on o.z" centers. for increased reliability, each module is burned in for 96 hours at +zsoc befo~e final test and shipment, . { :~1 digital j inputs i is.. no.. 11 i i i i bit ,. lsb strobe input - 13 z. . 165n. " . -isma 19 dia dutput lb deglitcher input 2., - amplifier 20 93!1 output 21 7s.n output son output 22 23 lo z output 16 - -ref out 15 -ref out .1sv 's.. no.. 2 notes, ,. inputs shown for igbit versions. for ."'t versions pins 11 and 12 are unused. 2. these parts '" are omitted in basic versions. but present in "a" versions. mdd series block diagram """"'t"'" t"ro ".., j\, ro~ rn""/cqtcpc: ilnl 1/ 1n-.~.q --- ---~ obsolete
specifications (typical at +25c and nominal supply voltages unless otherwise noted) model outline dimensions dimensions shown in inches and (mm). mdd-o820 mdd-o820a mdd-1o20 mdd-1o2oa resolution accuracy (including linearity) at maximum word rate of 20mhz monotonicity 8 bits 10 bits io.2% io.05% guaranteed 0 to + 70 c digital data bit inputs logic leveilload positive logic-binary (bin) 1 standard "s" ttl load "i" = +2.4v to +5v "0" = ov to +0.4v digital strobe input logic level/load positive logic risetime and falltime width timing frequency output voltage, no load, unipolar bipolar impedance pin 23, low z pin 22, 50n pin 21, 75n pin 20, 93n amplifier current dac current 2 standard "s" ttl loads "i" = +2.4v to +5v "0" = ov to +0.4v ions max 15ns min negative-going trailing edge to occur a minimum of 20ns after last data bit change 20m hz max mdd-o820 mdd-i0w 0 to +2v mdd-o820a mdd-i020a externally programmable with gain and offset resistors to il0v max +ivto-lv ion max 50n i5% 75n is% 93n i5% in max 50n il % 75n il % 93n il% i50ma for dc load = loon min, de load = zout + rload +15ma settling time dac current output (to 0.1%) voltage output isns sons to 0.1% 2v pop 120ns to 0.1 % 4v pop residual glitch 1 pedestal 30m v for 2v pop f.s. output or 1.5% of f.s. 1 om v for 2v pop f.5. output or 0.5% of f.s. output zero offset output zero offset vs. temp gain references available adjustable to zero l00ppm/oc adjustable i6.2v power requirements +15vi3% -15vi3% +5vi5% power supply rejection ratio case 120ma 150ma 2soma 0.1%/v diallyl phthalate (per mil-m-14 type sdg-f) temperature range operating storage 0 to +700c -55c to +8soc notes i occ:un at the update rate. specifications ..bject to ch...,e without notice. vol. ii, 10-40 digital-to-analog converters ~ l~ lo"",.>m>n j~ !0.50 00..,.0210>a~.:r "'>1"" " 1 1 i.4 22, " '" 11 h " 12 h ,. " bottom voew we>g"u~,'43g --11--0.",.641 "ns are golo 'la teo "r mil.q."" type n oot on top 'nd>ca tes posinon of "n ,. pin designations "all grounds internall y corrected -- -- pin function pin function 1 ground" 15 -ref out 2 bit 1 input (msb) 16 +ref out 3 bit 2 input 17 ground" 4 bit 3 input ib deglitcher input 5 bit 4 input 19 dia output 6 bit 5 input 20 93sl output 7 bit61nput 21 7511 output 8 bit 7 input 22 5oij output 9 bit 8 input 23 lo z output 10 nc 24 amp feedback 11 bit 9 input 25 ground" 12 bit 10 input (lsbi 26 -15v power input 13 strobe input 27 +15v power input 14 ground" 28 +5v power input obsolete
notes on "deglitching" an mdd series d/a converter operating with a full-scale p-p analog output of 1 v will typically have a glitch, or transient, in its output which is 15mv in amplitude and is 25ns wide, at the 50% points. these typical values are independent of whether the d/a converter is an 8-bit unit or a 10-bit unit. this glitch remains constant, regardless of the transition points. in other words, it is the same for the transition from 0000000001 to 1000000000 as it is for the transition from 1000000000 to 1000000001 or any other two input words. a constant glitch is the purpose of the deglitcher circuits. they are intended to hold the area under the curve at a con- stant value; they are not intended to get rid of all glitches per se. when the area under the transient curve is held constant, the frequency spectrum of the glitch is a fine line; i.e., a single- line spectrum at the sample rate frequency, and harmonics of the sample frequency. if the glitch is a function of signal dynamics, as it is in the case of a d/a converter output which is not deglitched, a multitude of intermodulation products art! formed. some of , peoesta~ -l- t \l- f - residual glitch figure 1. pedestal/glitch relationship data inputs (changing) z z z -j --.j '--- minimum 15ns maximum 65% of period - i 1 ~ of update rate !-50ns(min!-j i- minimum 20ns between last bit change and strobe trailing edge strobe input mdd-o820 or mdd-1020 output i approx. f !-40ns- v.... mdd-o820-a or mdd-1020-a output i - approx. r-60ns -1 figure 2. mdd series timing diagram r - - - ~s..o:, - - - --, 15 i i i :l6.2v i~ 1+ , / j current controlled by input digital code lo~oto+15ma -ref out 750q 16 19 +ref out dia output figure 3. d/a current equivalent circuit these 1m products appear in the video pass-band as spurious signals and increased noise level. the deglitcher circuits effec- tively eliminate these products. when they do, the sin ratio approaches that of an ideally-quantized signal, where the rms noise is qi.jli, when frequencies above nyquist are filtered out. in summary then: 8 the residual glitch for an mdd series d/a converter is typically 15m v for a full-scale iv p-p output; this is 1.5% off.s. 8 the glitch width is typically 25ns at the 50% points. 8 the amplitude and width of the glitch are constant, and independent of: -the magnitude of change in successive transitions -number of bits of digital output -input (update) data rates d/a converters without deglitching circuits have smaller, shorter glitches, on the average; but this type of converter has larger glitches at the major crossings, especially at the mid- scale transition. 1odb/div i 500khz/div figure 4. spectrum of to-bit d/a operating at 11 mhz update rate without deglitching - unfiltered "-. 1odb/div 5o0khz/div figure 5. spectrum of to-bit d/a operating at 11 mhz update rate with deglitching - unfiltered obsolete
figure 9. typical a/d-d/a back-to-back connections for video applications or testing the typical video differential phase and gain errors (disre- garding quantization effects) for the configuration shown are 3 and 3%, respectively, using an encode command frequency of three times the ntsc color subcarrier (l0.74mhz). for applications requiring digitization at frequencies of four times ntsc (14.32mhz) or three times pal (13.29mhz) the matv-0816.a/d converter should be substituted. for ap- plications requiringdigitization at four times pal (17. 74mhz), the matv-0820 aid converter should be substituted. results are applicable for either ntsc or pal test signals using the 20 ire modulated ramp. due to the inherently stable characteristics of the output oper- ational amplifier, the "a" versions are recommended for driving properly terminated video terminated lines. digital inputs msb bit 1 i i i i i i i i i bit 10 lsb lk } select output to match 20 of transmission line 16 +ref out 15 -ref out 19 diaoutput offset adj 25k 10k is oeglitcher input gainadj 93n output 21 75f! output n son output strobe input 13 23 lo 2 output vl ~oto+1v figure 6. unipolar output configuration basic versions digital inputs msb bit 1 i i i i i i i i i sit 10 lsb mdd.l02o deglitched 18 deglitcher input dia converter. 20 93!! output o } 51< 21 75n output select output 0 . to ma"rch zo of 22 son output transmission line 15 -ref out 19 dia output offset adj soon adjust for zero volts output with an input codeofloo 00 gain adj strobe input 23 lo z output 13 vl ' -0.5v to +0.5v figure 7. bipolar output configuration basic versions analog input analog ground encode command input encode ground digital signal processor, memory interface, etc. 9 +15v -15v +5v -5.2v ~ matv-osll 2 aid 12 converter i data 11 11 10122 ready . out vol. ii, 10-42 digital-to-analog converters -- ~- digital inputs offset adj msb bit 1 i i i i i i i i bit 10 lsb 75on 115 -ref out 0 to +2v 19 dia output deglitcher 18 input 750n 20 93n output 21 75'1 output select output } to match zo of line trans- mission 22 son output 23 lo z output strobe input 13 amplifier 24 feedback cee rgaon notes, ,. select rgain to give desired open circuit output voltage. the input voltage to the dp amp is approximately 0 to +2v. the output of the op amp is therefore ((2 x rgainii5oo'i1 volts p.p. 2. the logic is inverted internall y for the "a" versions such that all "i's" at the digital inputs yields a full.scale positive voltage at the dp amp output. 3. for positive unipolar operation, the nominal offset potentiometer resistance should be set for a value of approximatel y 800'1. making a 2000!! potentiometer ideal 4. for bipolar operation, the nominal offset potentiometer resistance should be set for a value of approximately 2300<2, making a 5000!! potentiometer ideal the output voltage should be adjusted for zero with an input code of 10. . . . . . . . 00. 5. make cfb nominally iopf. select for optimum settling time if desired. 6. if adjustable gain is desired, add a low-value, ldw.inductance cermet trimming potentiometer in series with rgain' by putting the gain adjustment here, the gain and offset adjustments are independent of each other. figure 8. output configuration - "a" versions 15 cfb 10pf gain aoj 2k +5v ordering informa non for 8-bit models, order: mdd-q826 without output amplifier mdd-q820a with output amplifier for lo-bit models, order: mdd-1020 without output amplifier mdd-1020a with output amplifier mating pin socket connectors for the mdd series is model msb-2. prototyping socket is msd-l. the mdd series d/a"s are normally burned-in at +2soc for a minimum of 96 hours. for extended burn-in, consult the factory. all of analog devices' data acquisition products are covered by a one-year warranty. obsolete
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